A Power Efficient System Design Methodology Employing Approximate Arithmetic Units

Tuba Ayhan; Firat Kula; Mustafa Altun

doi:10.1109/ISVLSI.2017.50

A Power Efficient System Design Methodology Employing Approximate Arithmetic Units

Tuba Ayhan, Firat Kula, Mustafa Altun

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Citations (Scopus)

Abstract

In this work a power efficient approximate system design methodology is introduced and its performance is demonstrated by a 2D-DCT implementation on Spartan 3 FPGA. The method is applicable to any system with arithmetic computation regardless of their architecture, because it utilizes the existing approximate arithmetic units. The novelty of the proposed method is its system analysis approach starting from the highest level and exploring through the sub-blocks down to the basic arithmetic units. It first evaluates a given system block diagram and sets the desired performance limits of each processing block to achieve the desired ultimate quality metric. Then, the arithmetic power consumption is minimized by employing the appropriate arithmetic units which are chosen by linear/non-linear programming with linear constraint solver. The tests on 2D-DCT implementation show a power reduction of 8% for a 0.01 dB PSNR loss for 128x128 images, on the average.

Original language	English
Title of host publication	Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Editors	Ricardo Reis, Mircea Stan, Michael Huebner, Nikolaos Voros
Publisher	IEEE Computer Society
Pages	243-248
Number of pages	6
ISBN (Electronic)	9781509067626
DOIs	https://doi.org/10.1109/ISVLSI.2017.50
Publication status	Published - 20 Jul 2017
Event	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 - Bochum, North Rhine-Westfalia, Germany Duration: 3 Jul 2017 → 5 Jul 2017

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2017-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Country/Territory	Germany
City	Bochum, North Rhine-Westfalia
Period	3/07/17 → 5/07/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

approximate adders
Approximate computing
DCT
JPEG encoder
low-power digital systems

Access to Document

10.1109/ISVLSI.2017.50

Cite this

Ayhan, T., Kula, F., & Altun, M. (2017). A Power Efficient System Design Methodology Employing Approximate Arithmetic Units. In R. Reis, M. Stan, M. Huebner, & N. Voros (Eds.), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 (pp. 243-248). Article 7987526 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2017.50

Ayhan, Tuba ; Kula, Firat ; Altun, Mustafa. / A Power Efficient System Design Methodology Employing Approximate Arithmetic Units. Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. editor / Ricardo Reis ; Mircea Stan ; Michael Huebner ; Nikolaos Voros. IEEE Computer Society, 2017. pp. 243-248 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI).

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abstract = "In this work a power efficient approximate system design methodology is introduced and its performance is demonstrated by a 2D-DCT implementation on Spartan 3 FPGA. The method is applicable to any system with arithmetic computation regardless of their architecture, because it utilizes the existing approximate arithmetic units. The novelty of the proposed method is its system analysis approach starting from the highest level and exploring through the sub-blocks down to the basic arithmetic units. It first evaluates a given system block diagram and sets the desired performance limits of each processing block to achieve the desired ultimate quality metric. Then, the arithmetic power consumption is minimized by employing the appropriate arithmetic units which are chosen by linear/non-linear programming with linear constraint solver. The tests on 2D-DCT implementation show a power reduction of 8% for a 0.01 dB PSNR loss for 128x128 images, on the average.",

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Ayhan, T, Kula, F & Altun, M 2017, A Power Efficient System Design Methodology Employing Approximate Arithmetic Units. in R Reis, M Stan, M Huebner & N Voros (eds), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017., 7987526, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2017-July, IEEE Computer Society, pp. 243-248, 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, North Rhine-Westfalia, Germany, 3/07/17. https://doi.org/10.1109/ISVLSI.2017.50

A Power Efficient System Design Methodology Employing Approximate Arithmetic Units. / Ayhan, Tuba; Kula, Firat; Altun, Mustafa.
Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. ed. / Ricardo Reis; Mircea Stan; Michael Huebner; Nikolaos Voros. IEEE Computer Society, 2017. p. 243-248 7987526 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Ayhan T, Kula F, Altun M. A Power Efficient System Design Methodology Employing Approximate Arithmetic Units. In Reis R, Stan M, Huebner M, Voros N, editors, Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. IEEE Computer Society. 2017. p. 243-248. 7987526. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). doi: 10.1109/ISVLSI.2017.50

A Power Efficient System Design Methodology Employing Approximate Arithmetic Units

Abstract

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Bibliographical note

Keywords

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