TY - GEN
T1 - A novel signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits
AU - Temel, Turgay
AU - Morgul, Avni
AU - Aydin, Nizamettin
PY - 2004
Y1 - 2004
N2 - A higher-radix algebra for full-addition of two numbers is described and realised by combining multi-valued logic min, max, literal and cyclic operators in terms disjoint terms. The latter operator is designed by using a current-mode threshold circuit while the other operator is realised by only voltage-mode switching circuits. The threshold circuit employed allows for much higher radices compared to architetures employing voltage-mode binary logic switching circuits as well as better mismatch properties compared to previous threshold circuits. Due to disjoint terms involved, multi-valued logic min and max operators can be replaced with ordinary ordinary transmission operation and addtion, respectively. Resultant a single-digit, radix-8 full-adder and its 3-bit counterpart voltage-mode circuits are realised and compared. The algorithm is also exploited for a multi-digit case and its HSPice simulation results are presented.
AB - A higher-radix algebra for full-addition of two numbers is described and realised by combining multi-valued logic min, max, literal and cyclic operators in terms disjoint terms. The latter operator is designed by using a current-mode threshold circuit while the other operator is realised by only voltage-mode switching circuits. The threshold circuit employed allows for much higher radices compared to architetures employing voltage-mode binary logic switching circuits as well as better mismatch properties compared to previous threshold circuits. Due to disjoint terms involved, multi-valued logic min and max operators can be replaced with ordinary ordinary transmission operation and addtion, respectively. Resultant a single-digit, radix-8 full-adder and its 3-bit counterpart voltage-mode circuits are realised and compared. The algorithm is also exploited for a multi-digit case and its HSPice simulation results are presented.
UR - http://www.scopus.com/inward/record.url?scp=13944265608&partnerID=8YFLogxK
U2 - 10.1109/DSD.2004.1333261
DO - 10.1109/DSD.2004.1333261
M3 - Conference contribution
AN - SCOPUS:13944265608
SN - 0769522033
SN - 9780769522036
T3 - Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004
SP - 80
EP - 87
BT - Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004
A2 - Selvaraj, H.
T2 - Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004
Y2 - 31 August 2004 through 3 September 2004
ER -