A novel reversible fault tolerant microprocessor design in AMS 0.35um process

M. Hüsrev Cilasun; Mustafa Altun

A novel reversible fault tolerant microprocessor design in AMS 0.35um process

M. Hüsrev Cilasun, Mustafa Altun

Department of Electronics and Communication Engineering

ASELSAN Inc.

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

In this study, reversible circuits are revisited to achieve extreme soft-defect awareness in classical CMOS circuits. Defect models in the literature are reviewed and defect scattering is analyzed. A reversible 8-bit full adder is designed in 12-bit block code domain. As a proof of concept, a pair of reversible ALUs are embedded into a microprocessor with block-code encoded data-path. The design is simulated in ams 0.35um process and a layout is obtained for tapeout.

Original language	English
Pages (from-to)	3147-3154
Number of pages	8
Journal	Istanbul University - Journal of Electrical and Electronics Engineering
Volume	17
Publication status	Published - 2017

Keywords

Fault Tolerance
Microprocessor
Reversible Computing

Cite this

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AB - In this study, reversible circuits are revisited to achieve extreme soft-defect awareness in classical CMOS circuits. Defect models in the literature are reviewed and defect scattering is analyzed. A reversible 8-bit full adder is designed in 12-bit block code domain. As a proof of concept, a pair of reversible ALUs are embedded into a microprocessor with block-code encoded data-path. The design is simulated in ams 0.35um process and a layout is obtained for tapeout.

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KW - Reversible Computing

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A novel reversible fault tolerant microprocessor design in AMS 0.35um process

Abstract

Keywords

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