A new neuron model suitable for low power VLSI implementation

Ozgur Erdener; Serdar Ozoguz

doi:10.1109/ELECO.2015.7394550

A new neuron model suitable for low power VLSI implementation

Ozgur Erdener, Serdar Ozoguz

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation in a 0.35 μm CMOS process, the circuit occupies low chip area and has very low power consumption during real time scale operation. These features make the circuit suitable for hybrid interface applications and large scale VLSI neuromorphic networks.

Original language	English
Title of host publication	ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	15-19
Number of pages	5
ISBN (Electronic)	9786050107371
DOIs	https://doi.org/10.1109/ELECO.2015.7394550
Publication status	Published - 28 Jan 2016
Event	9th International Conference on Electrical and Electronics Engineering, ELECO 2015 - Bursa, Turkey Duration: 26 Nov 2015 → 28 Nov 2015

Publication series

Name	ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering

Conference

Conference	9th International Conference on Electrical and Electronics Engineering, ELECO 2015
Country/Territory	Turkey
City	Bursa
Period	26/11/15 → 28/11/15

Bibliographical note

Publisher Copyright:
© 2015 Chamber of Electrical Engineers of Turkey.

Access to Document

10.1109/ELECO.2015.7394550

Cite this

Erdener, O., & Ozoguz, S. (2016). A new neuron model suitable for low power VLSI implementation. In ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering (pp. 15-19). Article 7394550 (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ELECO.2015.7394550

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title = "A new neuron model suitable for low power VLSI implementation",

abstract = "This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation in a 0.35 μm CMOS process, the circuit occupies low chip area and has very low power consumption during real time scale operation. These features make the circuit suitable for hybrid interface applications and large scale VLSI neuromorphic networks.",

author = "Ozgur Erdener and Serdar Ozoguz",

note = "Publisher Copyright: {\textcopyright} 2015 Chamber of Electrical Engineers of Turkey.; 9th International Conference on Electrical and Electronics Engineering, ELECO 2015 ; Conference date: 26-11-2015 Through 28-11-2015",

year = "2016",

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Erdener, O & Ozoguz, S 2016, A new neuron model suitable for low power VLSI implementation. in ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering., 7394550, ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering, Institute of Electrical and Electronics Engineers Inc., pp. 15-19, 9th International Conference on Electrical and Electronics Engineering, ELECO 2015, Bursa, Turkey, 26/11/15. https://doi.org/10.1109/ELECO.2015.7394550

A new neuron model suitable for low power VLSI implementation. / Erdener, Ozgur; Ozoguz, Serdar.
ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering. Institute of Electrical and Electronics Engineers Inc., 2016. p. 15-19 7394550 (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation in a 0.35 μm CMOS process, the circuit occupies low chip area and has very low power consumption during real time scale operation. These features make the circuit suitable for hybrid interface applications and large scale VLSI neuromorphic networks.

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Erdener O, Ozoguz S. A new neuron model suitable for low power VLSI implementation. In ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering. Institute of Electrical and Electronics Engineers Inc. 2016. p. 15-19. 7394550. (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering). doi: 10.1109/ELECO.2015.7394550

A new neuron model suitable for low power VLSI implementation

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