TY - GEN
T1 - A new architecture for Cellular Neural Network on reconfigurable hardware with an advance memory allocation method
AU - Tukel, Mehmet
AU - Yalcin, Mustak Erhan
PY - 2010
Y1 - 2010
N2 - In this study a discretized version of Cellular Neural Network (CNN) was implemented with an Hardware Description Language using forward Euler approximation. When the designs in literature were reviewed, it was seen that registers of the designs significantly affect occupied chip area. The introduced design is focused on reducing chip area by reducing register occupation while not causing design complexity or lack in processing speed. Block Random Access Memories (Block- RAMs) in Field Programmable Gate Arrays (FPGA) were used instead of register arrays, which were designed to handle the relationship of the neighborhood and input-output communication in previous designs. The proposed design does not require additional memory to store input image and states of the CNN. Storing, reading and updating image, also providing neighbor relations of image were done with the proposed method which includes an advance memory allocation, image partitioning and supplementary blocks for the relationship of the neighborhood. In order to reduce the chip area of Cellular Processors, cellular control was simplified. Cellular Processors which have similar arithmetic units with previous designs occupy less combinatorial part and significantly less registers. The advantage of this design is presented by comparing the proposed designs in literature.
AB - In this study a discretized version of Cellular Neural Network (CNN) was implemented with an Hardware Description Language using forward Euler approximation. When the designs in literature were reviewed, it was seen that registers of the designs significantly affect occupied chip area. The introduced design is focused on reducing chip area by reducing register occupation while not causing design complexity or lack in processing speed. Block Random Access Memories (Block- RAMs) in Field Programmable Gate Arrays (FPGA) were used instead of register arrays, which were designed to handle the relationship of the neighborhood and input-output communication in previous designs. The proposed design does not require additional memory to store input image and states of the CNN. Storing, reading and updating image, also providing neighbor relations of image were done with the proposed method which includes an advance memory allocation, image partitioning and supplementary blocks for the relationship of the neighborhood. In order to reduce the chip area of Cellular Processors, cellular control was simplified. Cellular Processors which have similar arithmetic units with previous designs occupy less combinatorial part and significantly less registers. The advantage of this design is presented by comparing the proposed designs in literature.
KW - Digital Cellular Neural Network
KW - Image processing
KW - Image processing hardware
KW - Parallel processing
UR - http://www.scopus.com/inward/record.url?scp=77952409733&partnerID=8YFLogxK
U2 - 10.1109/cnna.2010.5430316
DO - 10.1109/cnna.2010.5430316
M3 - Conference contribution
AN - SCOPUS:77952409733
SN - 9781424466795
T3 - 2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010
BT - 2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010
PB - IEEE Computer Society
T2 - 2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010
Y2 - 3 February 2010 through 5 February 2010
ER -