A Model Based Hardware Implementation of Traffic Regulator in ARINC-664 End System

ARINC Specification 664 Part 7 (ARINC-664) defines an Ethernet based deterministic network protocol that provides bounded delay and jitter using redundant communication among the avionics applications. Achieving the end-to-end bounded delay objectives requires that incoming Ethernet frames must be regulated according to the ARINC-664 standard. However, the standard does not specify the details of traffic shaping and scheduling mechanisms. FPGA is one of the most preferred implementation choices for ARINC-664 due to its low power consumption, low latency data transfer, and security advantages. Compared to time consuming FPGA development, a model based hardware design enables faster prototyping and testing environment. In this study, a Hardware Description Language (HDL) convertible simulation environment in Simulink is created for ARINC-664 End System (ES) traffic regulator with several scheduling algorithms, and their performance analysis is reported. In addition, a run-time configurable and hardware convertible dynamic traffic regulator is proposed.