A layered UVM based testbench design for SpaceWire

Ahmet Çaǧri Baǧbaba; Buse Ustaoǧlu; Inan Erdem; Berna Ors

doi:10.1109/ELECO.2015.7394599

A layered UVM based testbench design for SpaceWire

Ahmet Çaǧri Baǧbaba, Buse Ustaoǧlu, Inan Erdem, Berna Ors

Department of Electronics and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

The Universal Verification Methodology is a standard which is designed to enable creation of reusable, robust and interoperable verification IP and testbench components. In this work, we implemented layered UVM testbench for SpaceWire which is a spacecraft communication network based in part on the IEEE 1355 standard of communications. This design helps further analyzes of SpaceWire by testing different SpaceWire layers such as exchange layer and character layer. Transactions were used at all layer of protocol and user can make analysis, coverage collecting and debugging through this design. In the conclusion, all simulator results and details about Verification IP design were given.

Original language	English
Title of host publication	ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1164-1168
Number of pages	5
ISBN (Electronic)	9786050107371
DOIs	https://doi.org/10.1109/ELECO.2015.7394599
Publication status	Published - 28 Jan 2016
Event	9th International Conference on Electrical and Electronics Engineering, ELECO 2015 - Bursa, Turkey Duration: 26 Nov 2015 → 28 Nov 2015

Publication series

Name	ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering

Conference

Conference	9th International Conference on Electrical and Electronics Engineering, ELECO 2015
Country/Territory	Turkey
City	Bursa
Period	26/11/15 → 28/11/15

Bibliographical note

Publisher Copyright:
© 2015 Chamber of Electrical Engineers of Turkey.

Access to Document

10.1109/ELECO.2015.7394599

Cite this

Baǧbaba, A. Ç., Ustaoǧlu, B., Erdem, I., & Ors, B. (2016). A layered UVM based testbench design for SpaceWire. In ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering (pp. 1164-1168). Article 7394599 (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ELECO.2015.7394599

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Baǧbaba, AÇ, Ustaoǧlu, B, Erdem, I & Ors, B 2016, A layered UVM based testbench design for SpaceWire. in ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering., 7394599, ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering, Institute of Electrical and Electronics Engineers Inc., pp. 1164-1168, 9th International Conference on Electrical and Electronics Engineering, ELECO 2015, Bursa, Turkey, 26/11/15. https://doi.org/10.1109/ELECO.2015.7394599

A layered UVM based testbench design for SpaceWire. / Baǧbaba, Ahmet Çaǧri; Ustaoǧlu, Buse; Erdem, Inan et al.
ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering. Institute of Electrical and Electronics Engineers Inc., 2016. p. 1164-1168 7394599 (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Baǧbaba AÇ, Ustaoǧlu B, Erdem I, Ors B. A layered UVM based testbench design for SpaceWire. In ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering. Institute of Electrical and Electronics Engineers Inc. 2016. p. 1164-1168. 7394599. (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering). doi: 10.1109/ELECO.2015.7394599

A layered UVM based testbench design for SpaceWire

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