A High Speed 180 NM CMOS Cryogenic SAR ADC

Ahmet Suna; Ismail Cevik; Mustafa Berke Yelten

doi:10.1109/MMS.2018.8611968

A High Speed 180 NM CMOS Cryogenic SAR ADC

Ahmet Suna, Ismail Cevik, Mustafa Berke Yelten

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

In this paper, an 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) which can be operated between room temperature and 77K has been designed for transceivers which is aimed to be used in space communications. The design has been accomplished through UMC 180 nm complementary metal oxide semiconductor (CMOS) technology. The proposed SAR ADC offers high speed and high linearity due to its integer-based digital-to-analog converter architecture. Reference clock signal of the SAR ADC has been generated via a charge pump-based phase locked loop (CP-PLL). At room temperature, the proposed SAR ADC accomplishes an effective number of bits (ENOB) of 7.7, and a signal to noise and distortion ratio (SNDR) of 48.15 dB. At 77 K, it achieves an ENOB of 7.8 and a SNDR of 48.71 dB. As the temperature becomes lower, it can be observed that the performance of the proposed SAR ADC improves noticeably.

Original language	English
Title of host publication	2018 18th Mediterranean Microwave Symposium, MMS 2018
Publisher	IEEE Computer Society
Pages	116-119
Number of pages	4
ISBN (Electronic)	9781538671320
DOIs	https://doi.org/10.1109/MMS.2018.8611968
Publication status	Published - 2 Jul 2018
Event	18th Mediterranean Microwave Symposium, MMS 2018 - Istanbul, Turkey Duration: 31 Oct 2018 → 2 Nov 2018

Publication series

Name	Mediterranean Microwave Symposium
Volume	2018-October
ISSN (Print)	2157-9822
ISSN (Electronic)	2157-9830

Conference

Conference	18th Mediterranean Microwave Symposium, MMS 2018
Country/Territory	Turkey
City	Istanbul
Period	31/10/18 → 2/11/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Funding

This work was sponsored by the Technological Research Council of Turkey under the project TÜB˙TAK 1001 215E080.

Funders	Funder number
Technological Research Council of Turkey	TÜB˙TAK 1001 215E080

Keywords

analog-to-digital converter (ADC)
complementary metal oxide semiconductor (CMOS)
cryogenic
Successive approximation register (SAR)

Access to Document

10.1109/MMS.2018.8611968

Cite this

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title = "A High Speed 180 NM CMOS Cryogenic SAR ADC",

abstract = "In this paper, an 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) which can be operated between room temperature and 77K has been designed for transceivers which is aimed to be used in space communications. The design has been accomplished through UMC 180 nm complementary metal oxide semiconductor (CMOS) technology. The proposed SAR ADC offers high speed and high linearity due to its integer-based digital-to-analog converter architecture. Reference clock signal of the SAR ADC has been generated via a charge pump-based phase locked loop (CP-PLL). At room temperature, the proposed SAR ADC accomplishes an effective number of bits (ENOB) of 7.7, and a signal to noise and distortion ratio (SNDR) of 48.15 dB. At 77 K, it achieves an ENOB of 7.8 and a SNDR of 48.71 dB. As the temperature becomes lower, it can be observed that the performance of the proposed SAR ADC improves noticeably.",

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author = "Ahmet Suna and Ismail Cevik and Yelten, {Mustafa Berke}",

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AU - Cevik, Ismail

AU - Yelten, Mustafa Berke

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N2 - In this paper, an 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) which can be operated between room temperature and 77K has been designed for transceivers which is aimed to be used in space communications. The design has been accomplished through UMC 180 nm complementary metal oxide semiconductor (CMOS) technology. The proposed SAR ADC offers high speed and high linearity due to its integer-based digital-to-analog converter architecture. Reference clock signal of the SAR ADC has been generated via a charge pump-based phase locked loop (CP-PLL). At room temperature, the proposed SAR ADC accomplishes an effective number of bits (ENOB) of 7.7, and a signal to noise and distortion ratio (SNDR) of 48.15 dB. At 77 K, it achieves an ENOB of 7.8 and a SNDR of 48.71 dB. As the temperature becomes lower, it can be observed that the performance of the proposed SAR ADC improves noticeably.

AB - In this paper, an 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) which can be operated between room temperature and 77K has been designed for transceivers which is aimed to be used in space communications. The design has been accomplished through UMC 180 nm complementary metal oxide semiconductor (CMOS) technology. The proposed SAR ADC offers high speed and high linearity due to its integer-based digital-to-analog converter architecture. Reference clock signal of the SAR ADC has been generated via a charge pump-based phase locked loop (CP-PLL). At room temperature, the proposed SAR ADC accomplishes an effective number of bits (ENOB) of 7.7, and a signal to noise and distortion ratio (SNDR) of 48.15 dB. At 77 K, it achieves an ENOB of 7.8 and a SNDR of 48.71 dB. As the temperature becomes lower, it can be observed that the performance of the proposed SAR ADC improves noticeably.

KW - analog-to-digital converter (ADC)

KW - complementary metal oxide semiconductor (CMOS)

KW - cryogenic

KW - Successive approximation register (SAR)

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M3 - Conference contribution

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T3 - Mediterranean Microwave Symposium

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EP - 119

BT - 2018 18th Mediterranean Microwave Symposium, MMS 2018

PB - IEEE Computer Society

T2 - 18th Mediterranean Microwave Symposium, MMS 2018

Y2 - 31 October 2018 through 2 November 2018

ER -

A High Speed 180 NM CMOS Cryogenic SAR ADC

Abstract

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Bibliographical note

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Keywords

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