A High Speed 180 NM CMOS Cryogenic SAR ADC

Ahmet Suna, Ismail Cevik, Mustafa Berke Yelten

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Citations (Scopus)


In this paper, an 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) which can be operated between room temperature and 77K has been designed for transceivers which is aimed to be used in space communications. The design has been accomplished through UMC 180 nm complementary metal oxide semiconductor (CMOS) technology. The proposed SAR ADC offers high speed and high linearity due to its integer-based digital-to-analog converter architecture. Reference clock signal of the SAR ADC has been generated via a charge pump-based phase locked loop (CP-PLL). At room temperature, the proposed SAR ADC accomplishes an effective number of bits (ENOB) of 7.7, and a signal to noise and distortion ratio (SNDR) of 48.15 dB. At 77 K, it achieves an ENOB of 7.8 and a SNDR of 48.71 dB. As the temperature becomes lower, it can be observed that the performance of the proposed SAR ADC improves noticeably.

Original languageEnglish
Title of host publication2018 18th Mediterranean Microwave Symposium, MMS 2018
PublisherIEEE Computer Society
Number of pages4
ISBN (Electronic)9781538671320
Publication statusPublished - 2 Jul 2018
Event18th Mediterranean Microwave Symposium, MMS 2018 - Istanbul, Turkey
Duration: 31 Oct 20182 Nov 2018

Publication series

NameMediterranean Microwave Symposium
ISSN (Print)2157-9822
ISSN (Electronic)2157-9830


Conference18th Mediterranean Microwave Symposium, MMS 2018

Bibliographical note

Publisher Copyright:
© 2018 IEEE.


This work was sponsored by the Technological Research Council of Turkey under the project TÜB˙TAK 1001 215E080.

FundersFunder number
Technological Research Council of TurkeyTÜB˙TAK 1001 215E080


    • analog-to-digital converter (ADC)
    • complementary metal oxide semiconductor (CMOS)
    • cryogenic
    • Successive approximation register (SAR)


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