A Hardware Accelerator Design for Quaternion to Euler Angles Conversion

Serkan Şenel*, Ramazan Yençeri

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper describes a hardware accelerator design for converting quaternion to Euler angles using High Level Synthesis methodology. As a design methodology, automatic code generation from Simulink model, prototyping device, number representation, formulation, basic operators and basic functions are explained. A successful implementation is presented by giving validation and synthesis results.

Original languageEnglish
Title of host publicationICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems
Subtitle of host publicationTechnosapiens for Saving Humanity
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350326499
DOIs
Publication statusPublished - 2023
Event30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023 - Istanbul, Turkey
Duration: 4 Dec 20237 Dec 2023

Publication series

NameICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems: Technosapiens for Saving Humanity

Conference

Conference30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023
Country/TerritoryTurkey
CityIstanbul
Period4/12/237/12/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

Keywords

  • Euler angles
  • HDL code generation
  • HLS
  • High-level synthesis
  • quaternion

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