A chaotic time-delay sampled-data system and its implementation

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7 Citations (Scopus)


Chaotic time-delay systems are attractive candidates to generate chaotic dynamics because of their relatively simple system model. The circuit realization of the time-delay part is the main drawback of these systems. In order to overcome this drawback, a chaotic time-delay system which features a binary feedback function is presented. The use of binary feedback function results in a considerably simplified implementation of the time-delay unit based on using a flip-flop chain. Modeling the system thus obtained yields a chaotic sampled-data system. The existence of chaotic dynamics in the introduced sampled-data systems is numerically verified by calculating system Lyapunov exponents and applying a detailed bifurcation analysis. The chaotic attractor of the introduced sampled-data system is verified by the circuit realization of the system. In order to minimize the number of flip-flops in the chain while keeping the system in chaos, the spectrum of Lyapunov exponent versus clock frequency of the flip-flops and a bifurcation parameter is computed. The circuit realization of the introduced sampled-data system includes a relatively simple structure compared to other chaotic time-delay systems and this overcomes the complexity of the circuit implementation of the time-delay block.

Original languageEnglish
Article number1450039
JournalInternational Journal of Bifurcation and Chaos
Issue number3
Publication statusPublished - Mar 2014


  • circuit implementation
  • delay differential equations
  • Sampled-data system
  • time-delay system


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