Abstract
This paper presents a frequency multiplier employing a pseudo-differential charge-pump phase-locked loop (PDCPPLL) and a novel technique to maintain the 50% duty cycle at the output. A differential charge-pump PLL reduces the common-mode noise and alleviates unwanted secondary effects encountered in the single-ended architecture. Pseudo-differential PLLs do not involve common-mode feedback. Moreover, compared to single-ended counterparts, they offer improved noise suppression and leakage cancellation at the input of a voltage-controlled oscillator. A complete overview of the design will be provided along with simulations to prove its functionality and provide its sensitivity to process and temperature variations. The frequency multiplier is designed in 180 nm complementary-metal-oxide-semiconductor technology to operate at 560 MHz.
Original language | English |
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Title of host publication | PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 81-84 |
Number of pages | 4 |
ISBN (Electronic) | 9798350303209 |
DOIs | |
Publication status | Published - 2023 |
Event | 18th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023 - Valencia, Spain Duration: 18 Jun 2023 → 21 Jun 2023 |
Publication series
Name | PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings |
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Conference
Conference | 18th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023 |
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Country/Territory | Spain |
City | Valencia |
Period | 18/06/23 → 21/06/23 |
Bibliographical note
Publisher Copyright:© 2023 IEEE.
Keywords
- 50% duty cycle
- charge-pump phase-locked loop
- Frequency multiplier
- pseudo-differential