A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs

Hakan Cetinkaya; Ali Zeki; Alper Girgin; Enver Derun Karabeyoglu; Tufan Coskun Karalar

doi:10.1109/ICECS.2018.8618005

A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs

Hakan Cetinkaya, Ali Zeki, Alper Girgin, Enver Derun Karabeyoglu, Tufan Coskun Karalar

Department of Electronics and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Citations (Scopus)

Abstract

This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNR_jitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 μm × 360 μ m silicon area, is realized in a SiGe BiCMOS 0.13 μ m process.

Original language	English
Title of host publication	2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	277-280
Number of pages	4
ISBN (Electronic)	9781538695623
DOIs	https://doi.org/10.1109/ICECS.2018.8618005
Publication status	Published - 2 Jul 2018
Event	25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 - Bordeaux, France Duration: 9 Dec 2018 → 12 Dec 2018

Publication series

Name	2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

Conference

Conference	25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Country/Territory	France
City	Bordeaux
Period	9/12/18 → 12/12/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

clock level shifter
differential to single ended converter
LDOs
Non-overlap clock generation

Access to Document

10.1109/ICECS.2018.8618005

Cite this

Cetinkaya, H., Zeki, A., Girgin, A., Karabeyoglu, E. D., & Karalar, T. C. (2018). A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. In 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 (pp. 277-280). Article 8618005 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2018.8618005

Cetinkaya, Hakan ; Zeki, Ali ; Girgin, Alper et al. / A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 277-280 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

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title = "A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs",

abstract = "This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNRjitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 μm × 360 μ m silicon area, is realized in a SiGe BiCMOS 0.13 μ m process.",

keywords = "clock level shifter, differential to single ended converter, LDOs, Non-overlap clock generation",

author = "Hakan Cetinkaya and Ali Zeki and Alper Girgin and Karabeyoglu, {Enver Derun} and Karalar, {Tufan Coskun}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 ; Conference date: 09-12-2018 Through 12-12-2018",

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doi = "10.1109/ICECS.2018.8618005",

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series = "2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018",

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Cetinkaya, H, Zeki, A, Girgin, A, Karabeyoglu, ED & Karalar, TC 2018, A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. in 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018., 8618005, 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, Institute of Electrical and Electronics Engineers Inc., pp. 277-280, 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, Bordeaux, France, 9/12/18. https://doi.org/10.1109/ICECS.2018.8618005

A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. / Cetinkaya, Hakan; Zeki, Ali; Girgin, Alper et al.
2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 277-280 8618005 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNRjitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 μm × 360 μ m silicon area, is realized in a SiGe BiCMOS 0.13 μ m process.

AB - This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNRjitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 μm × 360 μ m silicon area, is realized in a SiGe BiCMOS 0.13 μ m process.

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Cetinkaya H, Zeki A, Girgin A, Karabeyoglu ED, Karalar TC. A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. In 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 277-280. 8618005. (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018). doi: 10.1109/ICECS.2018.8618005

A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs

Abstract

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Bibliographical note

Keywords

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