Abstract
In this work, a 1.5-b front-end sub-ADC with bootstrap and cross coupled adaptive power/ground switches and logics for a 11-b 1.6 GS/s sampling pipeline ADC is introduced. That 1.5-b sub-ADC avoids a dedicated sample-and-hold amplifier (SHA-less) to lower power dissipation. The design, totally, consuming 19.2 mA at a supply of 1.2 V, and, 7.2 mA at a supply of 1.6 V, occupying 156 μm × 205 μm silicon area, is realized in a SiGe BiCMOS 0.13 μm process.
Original language | English |
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Title of host publication | ELECO 2019 - 11th International Conference on Electrical and Electronics Engineering |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 518-521 |
Number of pages | 4 |
ISBN (Electronic) | 9786050112757 |
DOIs | |
Publication status | Published - Nov 2019 |
Event | 11th International Conference on Electrical and Electronics Engineering, ELECO 2019 - Bursa, Turkey Duration: 28 Nov 2019 → 30 Nov 2019 |
Publication series
Name | ELECO 2019 - 11th International Conference on Electrical and Electronics Engineering |
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Conference
Conference | 11th International Conference on Electrical and Electronics Engineering, ELECO 2019 |
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Country/Territory | Turkey |
City | Bursa |
Period | 28/11/19 → 30/11/19 |
Bibliographical note
Publisher Copyright:© 2019 Chamber of Turkish Electrical Engineers.
Funding
Scientific and Technological Research Council of Turkey (TUBfTAK) funds the project TUBITAK-1003, 115E752. The authors owe special thanks to Alper Girgin for doing top level layout routing. This work is also supported by MKR-IC.
Funders | Funder number |
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MKR-IC | |
Türkiye Bilimsel ve Teknolojik Araştirma Kurumu | TUBITAK-1003, 115E752 |