10-bit High-speed CMOS comparator with offset cancellation technique

Lida Kouhalvandi; Sercan Aygun; Gokhan Gunes Ozdemir; Ece Olcay Gunes

doi:10.1109/AIEEE.2017.8270524

10-bit High-speed CMOS comparator with offset cancellation technique

Lida Kouhalvandi, Sercan Aygun, Gokhan Gunes Ozdemir, Ece Olcay Gunes

Department of Electronics and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

Nowadays, in all modern electronic devices a low voltage with high speed comparator plays an important role in overall performance of the systems. This paper describes the implementation of a high-speed comparator with high-resolution, 10-bit, in 0.18pM CMOS technology drawn from a 1.8 V supply which is suitable for analog-to-digital converter (ADC) applications and for electronic industry. An offset cancellation technique is done and tested in order to decrease the offset and kickback noise. Regarding the Monte Carlo and corner simulation results for 100 samples and 9 corners respectively, it can be observed that bit error rate is approximately zero and comparator can response fast to the input signals. After accessing acceptable simulation results from designed comparator, the layout of each comparator components such as Op-amps, switches, and latch have been drawn and tested in Cadence Spectre Circuit Simulator.

Original language	English
Title of host publication	Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017
Editors	Andrejs Romanovs, Dalius Navakauskas, Armands Senfelds
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538641378
DOIs	https://doi.org/10.1109/AIEEE.2017.8270524
Publication status	Published - 2 Jul 2017
Event	5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017 - Riga, Latvia Duration: 24 Nov 2017 → 25 Nov 2017

Publication series

Name	Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017
Volume	2018-January

Conference

Conference	5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017
Country/Territory	Latvia
City	Riga
Period	24/11/17 → 25/11/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

high-speed comparator
latch
layout
Monte Carlo analysis
offset cancellation
op-amp
resolution

Access to Document

10.1109/AIEEE.2017.8270524

Cite this

Kouhalvandi, L., Aygun, S., Ozdemir, G. G., & Gunes, E. O. (2017). 10-bit High-speed CMOS comparator with offset cancellation technique. In A. Romanovs, D. Navakauskas, & A. Senfelds (Eds.), Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017 (pp. 1-4). (Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/AIEEE.2017.8270524

Kouhalvandi, Lida ; Aygun, Sercan ; Ozdemir, Gokhan Gunes et al. / 10-bit High-speed CMOS comparator with offset cancellation technique. Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017. editor / Andrejs Romanovs ; Dalius Navakauskas ; Armands Senfelds. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 1-4 (Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017).

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title = "10-bit High-speed CMOS comparator with offset cancellation technique",

abstract = "Nowadays, in all modern electronic devices a low voltage with high speed comparator plays an important role in overall performance of the systems. This paper describes the implementation of a high-speed comparator with high-resolution, 10-bit, in 0.18pM CMOS technology drawn from a 1.8 V supply which is suitable for analog-to-digital converter (ADC) applications and for electronic industry. An offset cancellation technique is done and tested in order to decrease the offset and kickback noise. Regarding the Monte Carlo and corner simulation results for 100 samples and 9 corners respectively, it can be observed that bit error rate is approximately zero and comparator can response fast to the input signals. After accessing acceptable simulation results from designed comparator, the layout of each comparator components such as Op-amps, switches, and latch have been drawn and tested in Cadence Spectre Circuit Simulator.",

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Kouhalvandi, L, Aygun, S, Ozdemir, GG & Gunes, EO 2017, 10-bit High-speed CMOS comparator with offset cancellation technique. in A Romanovs, D Navakauskas & A Senfelds (eds), Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017. Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017, vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017, Riga, Latvia, 24/11/17. https://doi.org/10.1109/AIEEE.2017.8270524

10-bit High-speed CMOS comparator with offset cancellation technique. / Kouhalvandi, Lida; Aygun, Sercan; Ozdemir, Gokhan Gunes et al.
Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017. ed. / Andrejs Romanovs; Dalius Navakauskas; Armands Senfelds. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-4 (Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Nowadays, in all modern electronic devices a low voltage with high speed comparator plays an important role in overall performance of the systems. This paper describes the implementation of a high-speed comparator with high-resolution, 10-bit, in 0.18pM CMOS technology drawn from a 1.8 V supply which is suitable for analog-to-digital converter (ADC) applications and for electronic industry. An offset cancellation technique is done and tested in order to decrease the offset and kickback noise. Regarding the Monte Carlo and corner simulation results for 100 samples and 9 corners respectively, it can be observed that bit error rate is approximately zero and comparator can response fast to the input signals. After accessing acceptable simulation results from designed comparator, the layout of each comparator components such as Op-amps, switches, and latch have been drawn and tested in Cadence Spectre Circuit Simulator.

AB - Nowadays, in all modern electronic devices a low voltage with high speed comparator plays an important role in overall performance of the systems. This paper describes the implementation of a high-speed comparator with high-resolution, 10-bit, in 0.18pM CMOS technology drawn from a 1.8 V supply which is suitable for analog-to-digital converter (ADC) applications and for electronic industry. An offset cancellation technique is done and tested in order to decrease the offset and kickback noise. Regarding the Monte Carlo and corner simulation results for 100 samples and 9 corners respectively, it can be observed that bit error rate is approximately zero and comparator can response fast to the input signals. After accessing acceptable simulation results from designed comparator, the layout of each comparator components such as Op-amps, switches, and latch have been drawn and tested in Cadence Spectre Circuit Simulator.

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ER -

Kouhalvandi L, Aygun S, Ozdemir GG, Gunes EO. 10-bit High-speed CMOS comparator with offset cancellation technique. In Romanovs A, Navakauskas D, Senfelds A, editors, Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1-4. (Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017). doi: 10.1109/AIEEE.2017.8270524

10-bit High-speed CMOS comparator with offset cancellation technique

Abstract

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Bibliographical note

Keywords

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